Where now for the transistor?

The transistor celebrated its 75th birthday on Friday (16 December), just at the point where its future is in doubt, or at least its role in the future scaling of the chips that use this now ubiquitous device.

Depending on who you ask, Moore’s Law is in various states of disrepair. Part of that problem is that the law itself is a bit underspecified so people naturally impress their own beliefs on it. While it was convenient, Intel pretended that it meant compute performance. Why? The company was pushing up clock speeds in a trend allowed by another of electronics’ informal laws, devised by IBM researcher Bob Dennard in the 1970s. A few years later that law slammed into the wall and Intel went back to talking about transistor density. Even that is a bit an illusion.

Though Gordon Moore put some meat on the bones a decade after writing about the trend he observed in the mid-1960s when the silicon industry was just getting underway, he was careful to talk vaguely about “functions” doubling every two years. That last bit was something of a revision as well because the early scaling trend was more annual than biennial.

Functions, however, provide a handy get-out clause for the next few decades because scaling is not going to happen the way it used to or at least seemed to. It’s just in time as the manufacturers’ names for their process nodes have become laughably separated from reality. That micrometre or nanometre measurement used to mean something: the length of the gate of the smallest transistor that could be made on that node. Technically, it was the drawn length as diffraction from the mask edges to the silicon surface made the resulting device slightly smaller. LSI Logic was notorious for exploiting that discrepancy whenever the company named its processes to make it look as though it had stolen a jump on the competition. Then everyone got in on the same act. 

Realising that they could not make the devices smaller in the same way forever they turned to other aspects of the chip design and scaled those instead. But they kept the same trend in naming to try to claim that the doubling in density with each generation was continuing. Things have got taller and rearranged in order to eke out every possible gain.

A case in point is some Imec’s work described at the International Electron Device Meeting (IEDM) a couple of weeks ago. The change seems almost trivial but it relies on some smart use of lithography techniques. The researchers added a level of interconnect that lies between the regular metal layers that carry many of the connections between transistors and the devices themselves. The trick was to use the same kind of pitch splitting that made it possible to get to feature sizes way below 100nm using 193nm-wavelength light. Chemical treatments use molecular-level self-alignment to form additional lines where the mask produces just one. With another mask to define where these lines get cut, you can define very fine, short-distance links between neighbouring transistors that reduce the amount of space taken up by the routing. The trick involves the cooperation of designers as it means the direction of routing of the first metal layer winds up being rotated 90° compared to where it would normally run. But the saving could be as much as 20 per cent, which few manufacturers will likely want to turn down.

At some point you just run out of nanometres, though that might be a generation or two beyond the point where the names run out of nanometres and someone has to dream up what to call the node beyond ‘1nm’. We are, notionally, already on 3nm, though the actual transistor gate is on the order of six or seven times that measurement.

The next step is to start stacking things. This is already happening with chiplets in multi-die packages. But it will also take place within the chips themselves with stacked transistors. It’s not exactly areal scaling as we used to know it but it is packing more into a smaller space, so if fits the law, more or less.

One key point about the original Moore’s Law was that scaling did not just make stuff smaller, it made it cheaper. Going 3D does not make things cheaper. They could get a lot more pricey with manufacturers hoping the likes of the hyperscalers and others will pay extra for the higher energy-efficiency and performance of packing chiplets as tightly as possible. Apple has exploited that with its Arm-based laptop and desktop computers.

But this is where we come back the to the word ‘functions’. They might not be transistors. We have seen 3D fabrication methods succeed in flash memories with stacks of memory cells close to a hundred deep thanks to chemical self-alignment techniques. That level of monolithic stacking is not going to be possible with the kind of computing circuitry found in today’s processors, but it might be used for other memories and other types of computation that can take advantage of regular, self-aligning structures. If they’re usable functions, they still count.

This type of design philosophy is where the industry needs to move from what’s known as design-technology co-optimisation – the kind of cooperation that makes Imec’s extra routing layer and rotation usable – to what Ann Kelleher, Intel’s executive vice president and general manager of Technology Development, called systems-technology co-optimisation in her keynote at IEDM. This takes the application as a starting point and works out what is needed to make it more efficient or run faster. Some neural networks, though not all, can take advantage of highly regular parallel arrays to run their extensive computations. Others might be taken care of by circuits that can be reconfigured on the fly. Though reconfigurability tends to eat up more space, if you can construct an array using regular, self-aligning building blocks such as those promised by some of the work in magnetic domain-wall structures, that may work out a lot denser than trying to use regular circuitry. The good old transistor will still be an important component over the next 75 years but maybe not quite as influential in the total system.